Electrostatic discharge (ESD) is a transient process of high-energy transfer from IC outside to inside when IC is floated. The entire discharge process takes about 100 ns for a human-body mode (HBM). In general, hundreds of volts, or even higher, are transferred during an ESD stress. Such a high voltage breaks down the gate oxide of the input stage and causes circuit malfunction. As the thickness of the gate oxide scales down continuously, it is important to provide a protection circuit or device to protect the gate oxide and to discharge ESD stress.
A conventional ESD protection circuit, as shown in FIG. 1 of the attached drawings, is a two-staged protection structure for digital ICs comprising a primary stage and a secondary stage. Between the primary stage and the secondary stage of the ESD protection circuit, a resistor is added to limit an ESD current flowing through a short-channel NMOS of the secondary stage. The resistance of the resistor depends on both the turn-on voltage of an ESD clamp device of the primary stage and the breakdown current of the short-channel NMOS of the secondary stage. Such a two-staged ESD protection circuit provides high ESD level for digital input pins. However, the large series resistance and the large junction capacitance in the ESD clamp devices cause a long RC timing delay to the input signal, and hence, it is not suitable for analog pins, especially for the RF signal applications.
In high frequency applications, the parasitic capacitance of ESD protection device degrades the power gain performance of radio frequency (RF) circuits. Heretofore, the parasitic capacitance is reduced by reducing area of the ESD protection device. However, reducing area also degrades the ESD level. There is a continuous endeavor to reduce the impact of the parasitic capacitance of ESD clamp devices for the RF circuits.
Several approaches are known to reducing parasitic capacitance while maintaining ESD level, including:                (1) Reverse-biased diodes with Vdd-to-Vss power clamp circuit: In this design, as shown in FIG. 2 of the attached drawings, a turn-on efficient ESD clamp circuit between the power rails is built into the ESD protection circuit to significantly increase the overall ESD level to compensate for the reduction of the ESD level caused by small area diodes.        (2) Inductor used as ESD device: Proposed by Leuven University, this design uses an LNA circuit with an inductor and Vdd-to-Vss dual stacked diodes to guard against ESD. An inductor is a low-pass passive device made of metal. Because the inductor connects the input to ground, it causes DC leakage from input directly to the ground. Therefore, a capacitor has to be used in series with the inductor to block input PAD and input gate. A problem with this design is that the inductor is used to protect the capacitor, instead of the input gate oxide.        (3) Distributed ESD protection device for high speed IC: Initially proposed by Stanford University, the circuit shown in FIG. 3 of the attached drawings can be extended to a multiple of stages of matching structure. The more stages are used, the better the power gain is. However, as it is difficult to evenly distribute the ESD current to all the stages, the first stage is always the first to suffer the ESD damage before the rest, which, in turn, causes a low ESD level in practice.        (4) Stacked reverse-biased diodes with Vdd-to-Vss power clamp circuit: The design, as shown in FIG. 4 of the attached drawings, employs a stack of series-connected reverse-biased diodes together with a Vdd-to-Vss power clamp circuit. Reports show that the ESD level of the stacked reverse-biased diodes does not degrade too much, while the parasitic capacitance of the ESD circuit is lowered.        
Since the above ESD protection circuits have disadvantages in providing effective ESD protection to an RFIC, it is desirable to have an ESD protection circuit that overcomes the deficiencies of the conventional designs and provide an effective protection to an RFIC.